Maxim DS33Z41 Manual do Utilizador descarregar pdf (Página 12)

DS33Z41DK

12 of 44

CONFIGURATION SWITCHES AND JUMPERS

The DS33Z41DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a

description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).

Table 2. Main Board PC Board Configuration

BASIC SETTING

SILKSCREEN

REFERENCE

FUNCTION

SW MODE HW MODE

DESCRIPTION

J45.9 + J45.10 Reserved Not installed —

This jumper is not for use with

the DS33Z41 design kit. Pin

J25.10 has been removed to

prevent accidental installation

J45.7 + J45.8 Enable device driver User decision —

When installed the device driver

will configure the DS33Z41 and

the Transceiver during power-up.

J45.5 + J45.6 Enable callbacks User decision —

When installed the driver will

respond to interrupts

J45.3 + J45.4 Select TCLK source User decision —

When installed the driver will

configure DS21458 TCLK to be

sourced from DS21458 RCLK.

When not installed DS21458

scaled MCLK is used. This

setting is only applied at reset. If

only one board is used select

TCLK = MCLK.

GROUND

(banana plug)

Power supply ground — —

System Ground. Always

connected to power supply.

VDD 3.3V

(banana plug)

Power supply VDD — —

System VDD. Always connected

to power supply.

OnCe BDM — — Debug connector for processor

DCEDTES

(3pos switch)

DS33Z41 mode pin;

DTE/DCE selection

LOW LOW Low for DTE

RMIIMII

(3pos switch)

DS33Z41 mode pin LOW LOW High for RMII, low for MII

CKPHA

(3pos switch)

DS33Z41 mode pin LOW LOW

SPI EEPROM hardware mode

configuration switch

MODEC0

(3pos switch)

DS33Z41 mode pin HIGH LOW Software mode selected

MODEC1

(3pos switch)

DS33Z41 mode pin LOW LOW Software mode selected

HWMODE

(3pos switch)

DS33Z41 mode pin LOW LOW

Hardware/software mode

(software mode selected)

SCANMO

(3pos switch)

DS33Z41 mode pin LOW LOW Set low for normal operation

SCANTRI

(3pos switch)

DS33Z41 mode pin LOW LOW Set low for normal operation

….testpoints…. DS33Z41 testpoints — —

Processor bus, JTAG and LAN

side testpoints for Zchip

Z-RESET (button) DS33Z41 reset — — System reset

A2, A1, A0

(3pos switches)

DS33Z41/SPI pins Mid position Mid position

Address pin/EEPROM config

switch. Set to mid position to

allow connection to processor.

SDRAM CLOCK

DS33Z41 SDRAM

clock

Installed Installed

100MHz oscillator to drive

SDRAM clock

MII CLOCK PHY MII clock Installed Installed

25MHz oscillator to drive SDRAM

clock

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 43 44

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