Maxim M30B Especificações Página 1

Rev: 102108 DS33M33 Demo KitGeneral Description The DS33M33 demo kit (DK) is an easy-to-use evaluation board for the DS33M33 and the DS33M33 Ethernet

_________________________________________________________________________________________________DS33M33DK Rev: 102108 10 of 48 11. Installing and R

_________________________________________________________________________________________________DS33M33DK Rev: 102108 11 of 48 12. Address Map Addre

_________________________________________________________________________________________________DS33M33DK Rev: 102108 12 of 48 12.2 Control and Sta

_________________________________________________________________________________________________DS33M33DK Rev: 102108 13 of 48 Register Name: GPIOAw

_________________________________________________________________________________________________DS33M33DK Rev: 102108 14 of 48 Register Name: DTOH_S

_________________________________________________________________________________________________DS33M33DK Rev: 102108 15 of 48 Register Name: RDOH_S

_________________________________________________________________________________________________DS33M33DK Rev: 102108 16 of 48 13. Additional Inform

_________________________________________________________________________________________________DS33M33DK Rev: 102108 17 of 48 14. Component List DE

_________________________________________________________________________________________________DS33M33DK Rev: 102108 18 of 48 CB50, CB56, CB57, CB6

_________________________________________________________________________________________________DS33M33DK Rev: 102108 19 of 48 J01, J30 2 HEADER,

_________________________________________________________________________________________________DS33M33DK Rev: 102108 2 of 48 Table of Contents 1.

_________________________________________________________________________________________________DS33M33DK Rev: 102108 20 of 48 JB09 1 CONN 2.1MM/5.5

_________________________________________________________________________________________________DS33M33DK Rev: 102108 21 of 21 Maxim cannot assume r

BEGINNING OF DS33M33DKDS33M33DK CONTENTS / INDEXADDR<13..0>DATA<7..0>WR_RWRD_DSM3X_ALECPLD_CSSPI_MISOSPI_SCKM3X_HIZ_NN6M3X_IFSEL_STYLEM3X_

M3XOH_ATOHM3XOH_ATOHSOFM3XOH_ATOHCLKCPLD_ATOHCPLD_RDOHVLDCPLD_ATOHSOFCPLD_ATOHCLKCPLD_DTOHCPLD_DTOHSOFCPLD_DTOHCLKCPLD_ATOHEN M3XOH_ATOHENM3XOH_TAOHEN

MOD0 IS GROUNDED IN THE SFPPULLUPS FOR OPEN DRAIN PINSTHIS SUBCIRCUIT IS FOR OBSERVATION AND LOOPBACK ONLYNOT FOR PRODUCTION USEPLACE / ROUTE CAPS AND

PULLUPS FOR OPEN DRAIN PINSTHIS SUBCIRCUIT IS FOR OBSERVATION AND LOOPBACK ONLYNOT FOR PRODUCTION USEPLACE / ROUTE CAPS AND TESTPOINTSUCH THAT THEY CA

30ETH_RX_ERRETH_RXD<7..0>01234567ETH_TXD<7..0>01233045673030GTXCLKM3X_LAN_CLKOM3X_LAN_CLKM3X_RMIISELM3X_DCESELETH_RX_CRSETH_COL_DETETH_MDI

USED IN RMII MODE (50 MHZ)ETH_REF_CLK IS ONLYCLKA AND CLKB TESTPOINTS ARE IN THE LIU BLOCKREFCLK & CLKC TESTPOINTS ARE IN THE PHY BLOCKCLOCK TESTP

FOR DDR11DDR_BA0DDR_BA1DDR_CASDDR_RASDDR_WEDDR_CKEDDR_CKDDR_CSDDR_CKINVDDR_LDMDDR_UDMDDR_LDQSDDR_UDQSDDR_DQ<15..0>DDR_DQ<15..0>DDR_VREFDDR

REMOVE THIS INVERTER TO MAKE USE OF THE JUMPER OPTIONS FOR ALE (ABOVE)AS TESTPOINTS FOR PROTO BOARD (NOT NEEDED)INSTANTIATE PULLUP FOR INT IN FPGAMT0

_________________________________________________________________________________________________DS33M33DK Rev: 102108 3 of 48 1. Board Floorplan Fig

DATABUS TAPS WRONG [0:7]THIS HAS BEEN FIXED IN THE FPGA.BUG FIX:PCB REV 01A0 HAD THEPLACE TESTPOINTS TO ALLOW LOOPBAK T--RPORT / PIN ASSIGNMENTSDS33M3

M33_GPIOA3M3X_CLKCM3X_CLKBM3X_CLKAM3X_CLADCLKM33_GPIOB2M33_GPIOB3M33_GPIOB1M33_GPIOA2M33_GPIOA1RESET_SYSCPLD_ATOHENCPLD_TAOHENCPLD_CSWR_RWCPLD_ATOHCLK

TRACE GEOMETRY FOR THIS IS: 1 INCH LONG, 10 MIL WIDE, 1 OZ COPPERBE LONG ENOUGH TO BUILD 0.05 OHM OF RESISTANCETO ENSURE LOAD SHARING BETWEEN THE 2.5V

MOUTING HARDWARE3.3V 1% REGULATOR10UF330POWEROK.1UF3.3V3.3V3.3VPOWEROK10UF68UF10UF0.0 0.00.068UF68UF10UF4.7UF.1UF.1UF4.7UF.1UF10UF4.7UF.1UF.1UF4.7UF.1

BEGINNING OF PROCESSOR HIERARCHY BLOCK212PD<31..0>OSC_MCUONCE_TCLKONCE_TRST_BONCE_TMSSPI_MOSITIM_16H_8LSPI_CSCS1EB01415222PA<22..0>GND1415

(NOT USED IN THIS DESIGN)NULL NETSD18 HAS A 10K LOAD TO GNDWHEN SET FORMASTER MODEFLASH ENABLEINTERNALFULL DRIVEBOOT INTERNALXTAL W/ PLLRESET CONFIGUR

DTR AND RTSCONNECTION ASBUT DO NOT POPULATEPLACE PADS FOR CAPVDD IS A(UNUSED) OUTPUTUSE RPACKTESTPOINTSON CP2101 CHIPALIGN KEYUART_DIGOUTPRT1_INPRT1_O

THIS MEMORY IS FORSERIAL BOOT (IF USED)19181721041251931302928261411910876324212018171610KSPI_SCK2523PD<31..16>13PA<19..0>27I3697_IORWPROC

CS_X1RD_DSWR_RWALE_DUT1A8^2CPUCLK_OUTPD<31..16>22161513654321131211106487590D_DUT<7..0>7097_IOCS_X3ENABLE_DRVENABLE_CLBKCS_X2INT4PROC_OSCI

V1_2V1_2.1UF.1UF10UFMEM_SCK10KL_TDO10K97_IO10UF.1UFMEM_SCKI23I15L_TMSL_TCKL_TDOL_TDII13I5MEM_CSMEM_SIMEM_SCK2.7VL_TDIL_TMSL_TCKI9L_TMSL_TCK10UFMEM_CSR

_________________________________________________________________________________________________DS33M33DK Rev: 102108 4 of 48 3. File Locations This

CONNECTORS FOR LAN MOTHERBOARD TO RESOURCE CARDBEGIN/END PHY CONNECTOR HIERARCHY BLOCKPHY_INTPT2_TX_CLKSFM-125-L2-S-D-LCGMII_CLKTOMAC_BUFLAN_CLKMDCRES

DS3254 ORALTERNATE_MCLK:REG CACR[AMCSEL1:0]=00 FOR 19.44MHZREG CACR[AMCSEL1:0]=10 FOR 77.76MHZBEGIN LIU HIERARCHY BLOCKRSTLIU_ALT_MCLKLIU_E3MCLK44.736

DS3254 ORPORT LOCATIONSRLOS1 IS AT PIN A1RLOS2 IS AT PIN M12IT IS A SPARE PORT IN THIS DESIGNDS3254 ORDS3253 IS RECOMMENDED FOR DS33M33PORT 4 OF DS325

UNUSED PRBS SIGNALSACCESS POINTS FOREND LIU HIERARCHY BLOCK332RXP1RXP4RXP2TXP2 TXP4RXP3TXP3RLOS4RLOS3PRBS3PRBS1PRBS4TTS3TTS1RTS310K10K 33033010KREDRED

MEM_SCK MUST BE AT PIN77 FOR TQFP144SIGNALS FORSIGNALS FORHIERARCHY INTERFACEBEGIN CPLD HIERARCHY BLOCKMEM_SICP_DUT_CLKC7654320DAT<7..0>V3_3GNDR

END CPLD HIERARCHY BLOCKMEM_SCK10K97_IO10K10K2.7V.1UFMEM_CSMEM_SOMEM_SII27I18L_TDIL_TDOL_TCKL_TMSCPU_RESETL_TMSL_TDOL_TDIL_TCKI12I3I710KMEM_SCK10UF10U

BEGIN PHY HIERARCHY BLOCKCLOSE TO PHYSTIPLINE TO V2_5PHYMAINTAIN 50OHMPLACE MDI RESISTORSPLACE 9.76K RESCLOSE TO BG_REFRXD[0:7] [PIN56:PIN45]TXD[0:7]

END PHY HIERARCHY BLOCKCAPS FOR DECOUPLEOF MX.+-STRAP OPTIONS HERE DO NOT FOLLOW DATASHEETCHECK THAT 2.2K RES USE THE SAME RPACK.1UF4.7UF4.7UF4.7UF4.7

_________________________________________________________________________________________________DS33M33DK Rev: 102108 5 of 48 4. Basic Operation Not

_________________________________________________________________________________________________DS33M33DK Rev: 102108 6 of 48 network traffic is sen

_________________________________________________________________________________________________DS33M33DK Rev: 102108 7 of 48 SILKSCREEN REFERENCE F

_________________________________________________________________________________________________DS33M33DK Rev: 102108 8 of 48 SILKSCREEN REFERENCE F

_________________________________________________________________________________________________DS33M33DK Rev: 102108 9 of 48 6. Line-Side Connectio