Maxim DS5001FP Guia do Utilizador descarregar pdf (Página 10)

DS5001FP

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Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this

configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system

with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The

bidirectional byte-wide data bus connects the data I/O lines of the SRAM.

Figure 5. CONNECTION TO 128k x 8 SRAM

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Maxim DS5001FP Guia do Utilizador Página 10