Maxim DS33Z41 Especificações descarregar pdf (Página 10)

Q7. What are some common problems and solutions when using the DS2155's internal HDLCs?

A7. The DS2155 SCT has the ability to transmit and receive packet data over a T1/E1 or J1 line. This device contains two

high-level, data-link controllers (HDLC), each of which can be configured for use with time slots, Sa bits (E1 mode), or the

FDL (T1 mode). Each controller has a 128-byte FIFO in the transmit and receive paths.

The most common problems are receiving incorrect data in the packets, not receiving enough data bytes in the packets,

or receiving a prematurely terminated (aborted) packet. Fortunately, for each controller, the DS2155 provides separate

registers that contain information about any errors that occur when receiving data. These registers provide a basis for

what action, if any, the system needs to perform for continuous normal operation.

The HDLC registers provide information on the following receive packet conditions: In Progress, Packet OK, CRC Error,

Abort, Overrun, and Message Too Short. The first condition, In Progress, means the HDLC is receiving a packet and no

alarms have been detected. Depending on the system, certain actions such as retrieving data from the FIFO may be

necessary. The second condition, Packet OK, means the HDLC received a correctly formatted packet, and the data has

been checked against the transmitted CRC bytes. The third condition, CRC Error, occurs when the calculated CRC for the

received data does not match the transmitted CRC bytes in the packet. The fourth condition, Abort, happens when the

HDLC receives the abort signal. The fifth condition, Overrun, occurs when the receive FIFO exceeds the maximum

capacity of 128 bytes. This usually indicates that the microcontroller did not read the FIFO data faster than the DS2155

writes the received data into the FIFO. The final condition, Message Too Short, indicates that 3 or fewer bytes, including

the CRC bytes, were received as a message.

The cause of some of the error conditions can be found by simple line testing, while others may require in-depth

knowledge of the system software. There are two main causes of CRC errors: either the transmission line quality is poor,

or there may be problems with the HDLC software/hardware on the transmit or receive side. Testing the line quality is

accomplished by performing a bit error-rate test while in remote loopback. If the line is not the problem, further

investigation into the HDLC software/hardware is required.

The Abort condition is difficult to solve because the cause is most likely on the transmit side, which may not be under the

designer's control. A common cause is a buffer under run condition in the transmit FIFO, which occurs when the transmit

HDLC needs to send data, but the processor has not written data into the FIFO. Sometimes, a faster processor solves the

problem, but changes often need to be made in the software/hardware. The DS2155 has special "watermark" registers

that the processor can use as indicators of the current FIFO status. The 'watermark' registers can be serviced in either a

polled mode or can be interrupt-driven to ease the processor load.

The Overrun condition is caused when the processor does not read data out of the receive FIFO as fast as the receive

HDLC writes data into the FIFO. Similarly, a faster processor may solve this problem, but again changes may need to be

made in the software/hardware. The DS2155 has special 'receive packet bytes available' and 'watermark' registers that

the processor can use as indicators of the current FIFO status. The 'receive packet bytes available' register is a simple

indication of how much data is currently in the FIFO, while the 'watermark' registers can be serviced or interrupt driven as

described above.

The Message Too Short condition is very easy to deal with—it is used to indicate that the HDLC packet received did not

contain enough data and, as such, is an illegal packet and should be ignored.

Q8. Why does the external loopback on the DS26401/DS2155 not work properly, though the

remote and payload loopbacks work fine?

A8. The cause for this error could be that you are not using the correct source for the transmit clock (TCLK) in the

DS26401. The DS26401DK was designed with three major components: a LIU, a framer, and a FPGA for specific signal

multiplexing. Unfortunately, the receive clock from the LIU goes to the DS26401 and a test-point header, but not to the

FPGA. Therefore, to perform an external loopback, you need a way to connect RCLK to TCLK.

Solution One Manually jumper RCLK and TCLK on the DS26401DK with the test-point headers. Make sure the TCLK

Solution Two You can control the source on the transmit clock with TCR3 register (TCR) using Bit 4 (TCSS0) and Bit 5

(TCSS1). Set TCSS0 and TSSC1 to a logic "1". This will cause the transmit clock to be the same as RCLK from the LIU.

Q9. What are the differences between the DS21455/DS21458 and the older DS21Q55?

A9. The DS21Q55 is a quad-port, 27mm x 27mm multichip module consisting of four independent DS2155 transceivers.

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